
Digital Design using VerilogHDL
VLSI Modeling, Coding and Verification
by Shilpi Birla, B.P. Singh, Neeraj Kumar Shukla
1st Edition
Publisher: Morgan Kaufmann
Book Details
| Print ISBN | 9780443290886 |
| eText ISBN | 9780443290893 |
| Publisher | Morgan Kaufmann |
| Publishing Year | 2026 |
| Edition | 1st Edition |
| Language | English |
| Pages | 650 |
Digital Design using VerilogHDL, 1st Edition provides a comprehensive theoretical and practical foundation in digital logic design and hardware circuit implementation. Intended for graduate students in electrical engineering, electronics engineering, and computer engineering, this volume establishes core concepts necessary for designing and analyzing modern digital circuits and systems.
The work is structured into two main parts, separating broad foundational principles from language execution: Part One on Digital Logic and Part Two on VerilogHDL. Early chapters focus on logic simplification and optimization methods required for efficient digital circuit synthesis. The material systematically addresses combinational logic and sequential logic integration within larger digital systems.
In its subsequent language coverage, the text provides thorough treatment of VLSI modeling, coding, and hardware circuit implementation. By connecting core logic structures directly to hardware description language applications, the text supports graduate engineering curricula focused on integrated circuit design and hardware verification.
Table of Contents
Chapter 1: Number Systems and their representation
Chapter 2: Logic family
Chapter 3: Combinational Circuits
Chapter 4: Arithmetic Circuits
Chapter 5: Sequential Circuits
Chapter 6: State Machines
Chapter 7: Memory Design
Chapter 8: Modeling in VerilogHDL
Chapter 9: VerilogHDL Coding and Testbench Verification
- • a. Logic Gates
- • b. Combinational Logic Circuits
- • c. Sequential Logic Circuits
- • d. Logic Integration using VerilogHDL
- • i. Adders
- • ii. Multiplexers
- • iii. Counters
- • iv. Registers
- • v. FSM
- • e. Synthesis of Logic
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